The present invention relates to the fabrication of ultra large scale integrated circuits and, more particularly, to an improved method for depositing a flow fill intermetallic dielectric on a wafer bearing these circuits.
The latest ultra large scale integrated circuits include features as small as about 0.5 microns and smaller. To effect contact with these features, the metallic contacts in the chip that contains the circuits must be stacked in three or more levels. These contacts are formed by a process that includes lithography and etch, and are separated by an intermetallic dielectric, typically SiO.sub.2. For successful lithography and etch in the formation of a second or subsequent level of metal, the substrate above which they are deposited must be substantially flat.
A process for depositing an SiO2 intermetallic dielectric with a substantially flat upper surface is described in C. D. Dobson. A. Kiermasz, K. Beekman and R. J. Wilby, Advanced SiO.sub.2 planarization using silane and H.sub.2 O.sub.2, Semiconductor International, December 1994, pp. 85-88; in M. Matsuura, Y. Hayashide, H. Kotani, T. Nishimura, H. Iuchi, C. D. Dobson. A. Kiemasz, K. Beekmann and R. Wilby,; and in A. Kiermasz, C. D. Dobson, K. Beekmann add A. H. Bar-Ilan, Planarization for sub-micron devices utilizing a new chemistry, DUMIC Conference, Feb. 21-22, 1995, pp. 94-100. These references are incorporated by reference for all purposes as if fully set forth herein. FIG. 1 schematically shows the "flow fill layer" 30 thus deposited between and around metallic contacts 22. Flow fill layer 30 includes a base layer 32, a flowlayer 34, and a cap layer 36. The essence of the process is the deposition of flowlayer 34, by reacting SiH.sub.4 and H.sub.2 O.sub.2 at 0.degree. C. to form a liquid layer, believed to be primarily Si(OH).sub.4 in composition. The liquid flows around and above metallic contacts 22, providing a dielectric layer with a substantially flat top surface. Base layer 32 of SiO.sub.2 is deposited, prior to the deposition of flowlayer 34, by plasma enhanced chemical vapor deposition (PECVD), to provide a surface to which flowlayer 34 adheres well. Cap layer 36 of SiO.sub.2 is deposited over flowlayer 34, also by PECVD, to protect flowlayer 34 in the final step: baking the wafer at a temperature of between 400.degree. C. and 450.degree. C. to transform flowlayer 34 from Si(OH).sub.4 to SiO.sub.2.
It is important that flowlayer 34 not have cracks. The transformation of Si(OH).sub.4 to SiO.sub.2 involves the evaporation of water as steam, which may induce the formation of cracks in flowlayer 34 as flowlayer 34 is transformed from a liquid to a solid. One of the purposes of cap layer 36 is to prevent the formation of these cracks. Cap layers 36 deposited by the processes known in the art have not been entirely successful in preventing crack formation. It also is important that the top surface of flow layer 30 be relatively flat. The processes known in the art have not entirely succeeded in achieving the desired degree of flatness.
There is thus a widely recognized need for, and it would be highly advantageous to have, a method of depositing a flow layer with a flatter top surface and less crack formation than in the prior art processes.